1. Field of the Invention
The present invention relates generally to methods for forming silicon nitride/silicon oxide (NO) layers typically employed within silicon oxide/silicon nitride/silicon oxide (ONO) dielectric layers within microelectronics fabrications. More particularly, the present invention relates to low oxidation temperature silicon nitride thermal oxidation methods for forming silicon nitride/silicon oxide (NO) layers typically employed within silicon oxide/silicon nitride/silicon oxide (ONO) dielectric layers within microelectronics fabrications.
2. Description of the Related Art
Common in the art of microelectronics fabrication is the use of silicon nitride/silicon oxide (NO) composite layers as dielectric layers. Silicon nitride/silicon oxide (NO) composite layers as dielectric layers within microelectronics fabrications are desirable since silicon nitride/silicon oxide (NO) composite layers often provide dielectric layers having improved dielectric properties in comparison with otherwise equivalent silicon oxide layers which are conventionally employed as dielectric layers within microelectronics fabrications.
Silicon nitride/silicon oxide (NO) composite layers may be formed within any of several types of microelectronics fabrications and also within any of several dielectric layer locations within the several types of microelectronics fabrications. Silicon nitride/silicon oxide (NO) composite layers may be formed within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, solar cell microelectronics fabrications, ceramic packaging microelectronics fabrications and flat panel display microelectronics fabrications.
Of the methods for forming silicon nitride/silicon oxide (NO) composite layers within microelectronics fabrications, a particularly common method is a thermal oxidation method where a silicon nitride layer is formed within a microelectronics fabrication and subsequently thermally oxidized through thermal annealing within an oxygen containing atmosphere to form a silicon nitride/silicon oxide (NO) layer. Typically, the silicon nitride layer from which is formed the silicon nitride/silicon oxide (NO) layer through the thermal oxidation method is formed through a thermal chemical vapor deposition (CVD) method at a temperature of from about 500 to about 800 degrees centigrade, while the thermal chemical vapor deposited (CVD) silicon nitride layer so formed is subsequently thermally annealed within the oxygen containing atmosphere at an appropriate thermal annealing temperature and for a sufficient thermal annealing exposure time to form from the silicon nitride layer the silicon nitride/silicon oxide (NO) layer with optimal dielectric properties for use within the microelectronics fabrication. Typical thermal annealing temperature and thermal annealing exposure time conditions which provide silicon nitride/silicon oxide (NO) layers within optimal dielectric properties within microelectronics fabrications include an 800-900 degrees centigrade thermal annealing temperature for a thermal annealing exposure time of greater than about 30 minutes.
Although silicon nitride/silicon oxide (NO) layers formed through thermal oxidation methods which employ thermal annealing of silicon nitride layers within oxygen containing atmospheres in accord with the foregoing thermal annealing conditions provide within microelectronics fabrications silicon nitride/silicon oxide (NO) layers with optimal dielectric properties, such silicon nitride/silicon oxide (NO) layers are often not formed entirely without problems within those microelectronics fabrications. In particular, it is known in the art of microelectronics fabrication that the elevated thermal annealing temperatures and extended thermal annealing exposure times through which silicon nitride layers are thermally annealed within oxygen containing atmospheres to form silicon nitride/silicon oxide (NO) layers within microelectronics fabrications are often sufficiently elevated and/or extended to compromise the integrity of other microelectronics structures and/or other microelectronics layers within a microelectronics fabrication within which is formed a silicon nitride/silicon oxide (NO) layer through the thermal oxidation method. Such other microelectronics structures and microelectronics layers may include, but are not limited to: microelectronics conductor structures and layers; microelectronics semiconductor structures and layers; and microelectronics insulator structures and layers. In particular, within integrated circuit microelectronics fabrications within which there are formed metal silicide conductor contact layers or metal silicide conductor contact structures, the foregoing thermal annealing temperatures and thermal annealing exposure times at which silicon nitride layers are thermally oxidized through thermal annealing within oxygen containing atmospheres to form silicon nitride/silicon oxide (NO) layers within integrated circuit microelectronics fabrications are often sufficiently elevated and/or extended to provide oxidation induced contact resistance deterioration or sheet resistance deterioration of those metal silicide conductor contact layers or metal silicide conductor contact structures.
It is thus in general towards forming within microelectronics fabrications silicon nitride/silicon oxide (NO) layers through thermal oxidation methods which employ thermal annealing of silicon nitride layers within thermally oxidizing atmospheres, such as oxygen containing atmospheres, while simultaneously avoiding thermal oxidation induced deterioration of other microelectronics layers and/or other microelectronics structures within those microelectronics fabrications that the present invention is generally directed.
Various methods have been disclosed in the art of integrated circuit microelectronics fabrication for forming novel nitride layers or novel nitride layer containing structures within those integrated circuits.
For example, Shuskus in U.S. Pat. No. 4,448,633 discloses a two-step plasma nitridation method for forming a nitride passivation layer upon the surface of a III-V (typically gallium arsenide) semiconductor substrate employed within an integrated circuit microelectronics fabrication. The first step within the two-step plasma nitridation method employs a comparatively low temperature to prevent semiconductor substrate surface decomposition and loss of the V component, while the second step within the two-step plasma nitridation method employs a comparatively higher temperature at which the plasma nitridation method proceeds more rapidly.
In addition, Bergemont, in U.S. Pat. No. 5,091,327 discloses a method for forming a high density stacked gate erasable programmable read-only memory (EPROM) split cell structure within an integrated circuit microelectronics fabrication, where the erasable programmable read-only memory (EPROM) split cell structure employs a silicon oxide/silicon nitride/silicon oxide (ONO) dielectric layer interposed between a floating gate and a control gate. Within the high density split gate erasable programmable read-only memory (EPROM) split cell structure formed through the method, there is eliminated bit line to bit line reach through.
Finally, Tseng, in U.S. Pat. No. 5,521,112 discloses a method for forming a stacked storage capacitor for use within a dynamic random access memory (DRAM) cell within an integrated circuit microelectronics fabrication, where the stacked capacitor may employ a silicon oxide/silicon nitride/silicon oxide (ONO) capacitive dielectric layer. Through the method there is formed within the dynamic random access memory (DRAM) cell within the integrated circuit microelectronics fabrication a stacked storage capacitor of increased areal capacitance.
Desirable in the arts of microelectronics fabrication are thermal oxidation methods employing thermal annealing within thermal oxidizing atmospheres, such as oxygen containing atmospheres, for forming silicon nitride/silicon oxide (NO) layers from silicon nitride layers within microelectronics fabrications while simultaneously avoiding thermal oxidation induced deterioration of other microelectronics layers and/or other microelectronics structures within those microelectronics fabrications. More particularly desirable in the art of integrated circuit microelectronics fabrication are thermal oxidation methods employing thermal annealing within thermal oxidizing atmospheres, such as oxygen containing atmospheres, for forming silicon nitride/silicon oxide (NO) layers from silicon nitride layers within integrated circuit microelectronics fabrications while simultaneously avoiding thermal oxidation induced deterioration of other integrated circuit layers and/or other integrated circuit structures, such as but not limited to metal silicide conductor contact layers and metal silicide conductor contact structures, within those integrated circuit microelectronics fabrications. It is towards the foregoing goals that the present invention is more specifically directed.